Double patterning is a technology developed for lithography to enhance the feature density. Typically, for forming features of integrated circuits on wafers, lithography technology is used, which involves applying a photo resist, and defining patterns on the photo resist. The patterns in the patterned photo resist are first defined in a lithography mask, and are defined either by the transparent portions or by the opaque portions in the lithography mask. The patterns in the patterned photo resist are then transferred to the underlying features.
With the increasing down-scaling of integrated circuits, the optical proximity effect posts an increasingly greater problem. When two separate features are too close to each other, the optical proximity effect may cause the features to short to each other. To solve such a problem, double patterning technology is introduced. The features closely located are separated to two masks, with both masks used to expose the same photo resist. In each of the masks, the distances between features are increased over the distances between features in the otherwise single mask, and hence the optical proximity effect is reduced, or substantially eliminated.
However, double patterning technology cannot solve native conflict problems. For example, referring to FIG. 1, features 2, 4, and 6 are closely located with both distances S1 and S2 being small enough to cause the optical proximity effect. Therefore, the double patterning technology is used to increase the distances between features 2, 4, and 6. In this situation, regardless of how features 2, 4, and 6 are distributed to two masks of a double patterning mask set, there will always be a mask, in which there are two of the features 2, 4, and 6. Accordingly, there will be at least one distance S1 or S2 existing in the mask.
The native conflict can be avoided by carefully laying out circuits. However, this can be done without much difficulty at the cell level. When the cells, which may be free from native-conflict and free from rule violations, are put into the hierarchy of the circuits, the boundary features in neighboring cells may be too close to each other, and hence conflicts occur at this level. In other words, there is no guarantee that the double-patterning rule compliance is still satisfied when the cells are integrated. For example, referring to FIG. 2, there are two standard cells 10 and 12, with each of the standard cells 10 and 12 being native-conflict free. The patterns in FIG. 2 having different shadings are in different double patterning masks. When standard cells 10 and 12 abut to each other, as shown in FIG. 3, feature 14 in cell 10 will be to close to feature 16 in cell 12. Since features 14 and 16 are in a same mask, the layout of features 14 and 16 violates design rules. This problem is difficult to solve since even if a re-layout may be performed on cells 10 and 12 to solve the conflict between cells 10 and 12, there may be a ripple effect, which means other new conflicts may be generated between each of cells 10 and 12 and other abutted cells. Particularly, cells 10 and 12 are standard cells that may be used in many circuits in the same chip and in other chips. It is very difficult to predict the possible conflict that may occur to cells 10 and 12. What is needed, therefore, is a method and structure for overcoming the above-described shortcomings in the prior art.